`timescale 10ns / 10ns

module key_led_tb ();

    reg clk_50m, rst_n;
    reg [3:0] key;

    initial begin
        $dumpfile("output/key_led_tb.vcd");
        $dumpvars(0, key_led_tb);
    end

    initial begin
        clk_50m = 0;
        rst_n = 0;
        #10 rst_n = 1;
        #10 key = 4'b0001;
        #5_000_000 key = 4'b0010;
        #5_000_000 key = 4'b0100;
        #5_000_000 key = 4'b1000;
        #5_000_000 key = 4'b000;
        #5_000_000 $stop;
    end

    always #1 clk_50m <= ~clk_50m;

    key_led # (
        .T              (100_000)
    )
    key_led_inst (
        .clk_50m        (clk_50m),
        .rst_n          (rst_n),
        .key            (key)
    );

endmodule  //key_led_tb